1. Field of the Invention
The present invention relates to a design technique for a semiconductor device. In particular, the present invention relates to a design technique for a semiconductor device having a contact structure.
2. Description of Related Art
In a manufacturing process of a semiconductor device, an interconnect structure may not be manufactured as expected. That is, physical parameters such as a width and a thickness of an interconnection, a thickness of an interlayer insulating film and the like may vary from their desired design values. Such manufacturing variability affects delay in a circuit. Thus, even if a designed circuit passes timing verification on a computer, an actual product may malfunction since the manufacturing variability occurs. Therefore, it is desirable to perform the timing verification in consideration of the manufacturing variability (refer, for example, to Japanese Laid-Open Patent Application JP-2007-172258).
Meanwhile, to consider the manufacturing variability during the timing verification means that a condition to be met in the timing verification becomes stricter. As the condition becomes stricter, the timing verification is more likely to result in fail and thus the number of circuit design modification times increases. This causes increase in a design TAT (Turn Around Time).
Japanese Laid-Open Patent Application JP-2006-209702 discloses a technique that can suppress increase in the design TAT while considering the manufacturing variability. According to the technique, unrealistic patterns of the manufacturing variability are excluded from consideration. For example, let us consider a case where a width and a thickness of an interconnection can vary from respective design values in a range from −3σ to +3σ (σ: standard deviation). In this case, a probability that both the width and thickness “simultaneously” vary to the maximum extent is extremely low from a statistical point of view. If such extreme situations are taken into consideration, it is necessary to support those extreme situations, which causes increase in the number of circuit design modification times. Therefore, according to the technique, such the extreme situations are excluded from the consideration (this scheme is hereinafter referred to as “statistical relaxation”. More specifically, the statistical relaxation is applied to calculation of corner conditions under which an interconnect delay becomes maximum or minimum. Then, interconnect resistance and interconnect capacitance under the corner conditions are provided as a library. This library is referred to in LPE (Layout Parameter Extraction). Consequently, it is possible to perform the timing verification in consideration of the manufacturing variability while excluding the extreme situations. In other words, it is possible to perform high-accuracy timing verification while preventing unnecessary increase in the design TAT.
Japanese Laid-Open Patent Application JP-2008-028161 also discloses a method of designing a semiconductor device in consideration of the statistical relaxation. First, correction parameters indicating variations of interconnect resistance and parasitic capacitance from design values due to the manufacturing variability are calculated. At this time, the correction parameters are calculated based on the above-described statistical relaxation scheme. Next, the LPE is performed based on a layout of the semiconductor device and thereby the interconnect resistance and parasitic capacitance related to an interconnection in the layout are extracted. After the LPE is completed, the extracted interconnect resistance and parasitic capacitance are respectively corrected by using the above-mentioned correction parameters. The post-correction interconnect resistance and parasitic capacitance are used for operation verification of the semiconductor device.
By the way, a contact structure is used in a semiconductor device for connecting between an interconnection formed in an interconnection layer and a transistor formed on a semiconductor substrate. The contact structure is so formed as to penetrate through an interlayer insulating film between the interconnection and the transistor.
Here, the inventor of the present application has recognized the following points. With increasing miniaturization of a semiconductor device in recent years, an interval between adjacent contact structures is getting narrower. Such tendency is conspicuous, for example, in a memory macro in which a large number of cell transistors are integrated. When the interval between adjacent contact structures becomes narrower, influence of the manufacturing variability of the contact structure on the parasitic capacitance is considered to become significant and nonnegligible. It is therefore desirable in designing a semiconductor device to consider the influence of the manufacturing variability of the interconnection as well as the contact structure.